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ZL9117M
Electrical Specifications V DD = 12V, T A = -40°C to +85°C unless otherwise noted. Typical values are at T A = +25°C. Boldface limits
apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
TYP
MAX
PARAMETER
CONDITIONS
(Note 14) (Note 15) (Note 14)
UNIT
OSCILLATOR AND SWITCHING CHARACTERISTICS (Note 16)
Switching Frequency Range
500
571
1000
kHz
Maximum PWM Duty Cycle
Minimum SYNC Pulse Width
Input Clock Frequency Drift Tolerance
Factory setting
External clock source
95
150
-13
–
–
–
–
–
13
%
ns
%
LOGIC INPUT/OUTPUT CHARACTERISTICS (Note 16)
Logic Input Bias Current
Logic Input Low, V IL
Logic Input High, V IH
Logic Output Low, V OL
Logic Output High, V OH
EN, PG, SCL, SDA pins
I OL ≤ 4mA (Note 22)
I OH ≥ -2mA (Note 22)
-10
–
2.0
–
2.25
–
–
–
–
–
10
0.8
–
0.4
–
μA
V
V
V
V
FAULT PROTECTION CHARACTERISTICS (Note 16)
UVLO Threshold Range
UVLO Set-point Accuracy
UVLO Hysteresis
Configurable via I 2 C/SMBus
Factory setting
2.85
-150
–
–
–
3
16
150
–
V
mV
%
UVLO Delay
Configurable via I 2 C/SMBus
0
–
–
–
100
2.5
%
μs
Power-Good V OUT Threshold
Power-Good V OUT Hysteresis
Power-Good Delay (Note 21)
VSEN Undervoltage Threshold
VSEN Overvoltage Threshold
Factory setting
Factory setting
Configurable via I 2 C/SMBus
Factory setting
Configurable via I 2 C/SMBus
Factory setting
–
–
0
–
0
–
90
5
–
85
–
115
–
–
200
–
110
–
% V OUT
%
ms
% V OUT
% V OUT
% V OUT
VSEN Undervoltage Hysteresis
Configurable via I 2 C/SMBus
0
–
–
5
115
–
% V OUT
% V OUT
VSEN Undervoltage/Overvoltage Fault Response
Time
Thermal Protection Threshold
(Controller Junction Temperature)
Thermal Protection Hysteresis
Factory setting
Configurable via I 2 C/SMBus
Factory setting
Configurable via I 2 C/SMBus
–
5
–
-40
–
16
–
125
–
15
–
60
–
125
–
μs
μs
°C
°C
°C
NOTES:
14. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
15. Parameters with TYP limits are not production tested unless otherwise specified.
16. Parameters are 100% tested for internal controller prior to module assembly.
17. V OUT measured at the termination of the FB+ and FB- sense points.
18. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to
approximately 2ms, where in normal mode it may vary up to 4ms.
19. Precise ramp timing mode is only valid when using the EN pin to enable the device rather than PMBus enable.
20. The devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable
signal.
21. Factory setting for Power-Good delay is set to the same value as the soft-start ramp time.
22. Nominal capacitance of logic pins is 5pF.
23. This condition is tested on the Intersil 3-module evaluation board at +50°C ambient temperature and 400LFM air flow.
24. The load current is related to the thermal derating curves. The maximum allowed current is derated while the output voltage goes higher than 2.5V.
7
FN7914.3
July 22, 2013
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